1. Field of Invention
The present invention relates to a dynamic random access memory made to have high integration density and low critical dimension and the method for making the same, and more specifically relates to a dynamic random access memory with planar upper-plate, low photoresist aspect ratio of bitline contacts, and low step height between periphery and cell arrays and method for making the same.
2. Description of the Related Art
The DRAM technology develops rapidly. The utilization and markets of DRAM further push the development of science and technology. The MOSFET IC (Metal-Oxide-Semiconductor Field-Effect-Transistor Integrated Circuit) is one of the main integrated circuit products. The production method basically comprises the steps of forming an insulated field oxide on silicon wafer and then producing a field-effect-transistor on the silicon wafer. In order to reduce the cost, the issue for increasing memory chip numbers per unit of wafer area and reducing memory chip area is more important. The decreasing of critical dimension becomes a greater challenge. The difficulties in the process, for example, spectrometric effects and molecular chemistry effects, are increasing because of the decreasing of critical dimension, for instance, from 0.25 xcexcm to 0.19 xcexcm.
The manufacturing of the metal contact has not influenced the whole DRAM production process until the pattern dimension decreases. The surface area of the capacitor and capacitance must be enhanced under the limited surface area as the integration density increases. In order to attain enough capacitance and excellent performance under the limited planar surface area, the three-dimensional structures are practical solutions. However, the three-dimensional structures, for example, the vertical and stacked capacitor, will result in difficulties during producing processes. The increasing step height and aspect ratio not only challenge producing processes, but also result in variations of critical dimension, and will influence throughput and yield. In order to solve such problems, various ways have been proposed to produce high integration density memory under the limited space. For example, U.S. Pat. No. 5,120,674 has disclosed a method of making a stacked capacitor DRAM cell; U.S. Pat. No. 5,214,603 has disclosed a folded bitline, ultra-high density DRAM having access transistors stacked above trench storage capacitors; U.S. Pat. No. 5,578,850 has disclosed a vertically oriented DRAM structure which replaces the conventional planar transistors; U.S. Pat. No. 5,387,533 has disclosed a method of making DRAM which has a dual cell plate structure made by forming two field insulation films with a constant interval on a semiconductor substrate and forming word lines uniformly spaced from each other along with the associated bit lines; U.S. Pat. No. 5,736,761 has disclosed a DRAM cell arrangement and method for manufacturing it, which can be utilized in 1 Gbit generation.
Conventional methods of upper-plate etching in capacitor-under-bitline DRAM (CUB DRAM) are facing patterning challenges on critical dimension control, mis-alignment high step height. In order to overcome the upper-plate patterning difficulties, many techniques, such as thin resist and multiple exposure, were proposed for the plate formation. However, much more difficulty was found in the plate etching while step height increases rapidly. As shown in FIG. 1, for a structure of the conventional capacitor-under-bitline DRAM, high step height and high photoresist aspect ratio are critical issues to be solved. In order to gain the capacitance and surface formed by the hemisphere grain and high dielectric constant substance 91, the three-dimensional structures cause the height differences deposited by the upper-plate 13 to be almost 1 xcexcm, especially at the interface between peripheral circuit and cell arrays. The thickness of the following photoresist coating should be about 1 xcexcm in order to make the masked photoresist area 12 resist etching of the following process. In consequence, the depth of the unmasked photoresist area 11 almost reaches 2 xcexcm. Such high photoresist aspect ratio of contact makes the exposure and development of the bitline contacts almost impossible, especially when the integration density of the contact increases and the critical dimension of the contact decreases, for example, 0.25 xcexcm. The exposure light and developer is hard to reach the bottom of the bitline contacts, and thus proceeding processes will be influenced.
An object of the present invention is to provide a novel and practical DRAM which effectively decreases the photoresist aspect ratio during producing bitline contacts and further obtains clear and precise patterns of the bitline contacts in confined linewidth and thus increases integration density of the memory.
Another object of the present invention is to decrease the step height at the interface between peripheral circuit and cell arrays. The poor coating problem occurring at peripheral circuit because of high step height could be solved. Furthermore, there is a lightly doped polysilicon layer between the lower-plate and the silicon wafer substrate. The lightly doped polysilicon layer prevents the lower-plate from current leakage, large energy consumption and signal interruption.
A further object of the present invention is to provide a novel and practical method for making DRAM. The processes for making the capacitor and bitline contacts could avoid the disadvantages mentioned hereinbefore.
A still further object of the present invention is to provide a novel and practical method for making DRAM by which the current leakage would not occur between the lower-plate and the silicon wafer substrate.
To achieve the objects mentioned above, the present invention discloses a novel DRAM which has a planar upper-plate. Furthermore, the upper-plate of the DRAM has an opening broader than the contact at the top of the lower-plate neighboring the bitline contacts. And, the step height at the interface between the peripheral circuit and cell arrays almost does not exist.
To achieve the objects mentioned above, the present invention discloses a novel method for making DRAM. In the method, an oxide plug is formed at bitline contacts when producing the capacitor-under-bitline DRAM. Furthermore, the upper-plate of the DRAM forms a broader opening than the contact at the top of the lower-plate neighboring the bitline contacts in order to decrease the photoresist aspect ratio and to release the critical requirements of the bitline contacts process. The process window could be expanded and both throughput and yield could be improved.
Furthermore, the present invention discloses a method for making DRAM by which a thick oxide layer is deposited on the peripheral circuit to the extent that the thick oxide layer is almost as high as the lower-plate in order to solve the problems of step height and poor coating at the interface between the peripheral circuit and cell arrays.
To avoid the current leakage between the lower-plate and the silicon wafer substrate, the present invention discloses a method by which a lightly doped polysilicon layer is deposited before depositing the lower-plate.
The present invention will be elucidated with reference to the accompanying Drawings which, however, are being presented for illustrative purpose.